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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order Number: MPC9331/D Rev 4, 02/2003
3.3V 1:6 LVCMOS PLL Clock Generator
The MPC9331 is a 3.3V compatible, 1:6 PLL based clock generator targeted for high performance low-skew clock distribution in mid-range to high-performance telecom, networking, and computing applications. With output frequencies up to 240 MHz and output skews less than 150 ps, the device meets the needs of most the demanding clock applications. The MPC9331 is specified for the temperature range of 0C to +70C. Features * 1:6 PLL based low-voltage clock generator
MPC9331
LOW VOLTAGE 3.3V LVCMOS 1:6 CLOCK GENERATOR
* * * * * * * *
3.3V power supply Generates clock signals up to 240 MHz Maximum output skew of 150 ps Differential LVPECL reference clock input Alternative LVCMOS PLL reference clock input Internal and external PLL feedback Supports zero-delay operation in external feedback mode
PLL multiplies the reference clock by 4x, 3x, 2x, 1x, 4/3x, 3/2x, 2/3x, x/2, x/3 or x/4 * Synchronous output clock stop in logic low eliminates output runt pulses
Pin and function compatible to the MPC931 Functional Description The MPC9331 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the MPC9331 requires either the selection of internal PLL feedback or the connection of one of the device outputs to the feedback input to close the PLL feedback path in external feedback mode. The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. In external PLL feedback configuration and with the available post-PLL dividers (divide-by-2, divide-by-4, and divide-by-6), the internal VCO of the MPC9331 is running at either 2x, 4x, 6x, 8x, or 12x of the reference clock frequency. In internal feedback configuration (divide-by-8) the internal VCO is running 8x of the reference frequency. The frequency of the QA, QB, QC output banks is a division of the VCO frequency and can be configured independently for each output bank using the FSELA, FSELB, and FSELC pins, respectively. The available output to input frequency ratios are 4x, 3x, 2x, 1x, 4/3x, 3/2x, 2/3x, x/2, x/3, or x/4. The REF_SEL pin selects the differential LVPECL or the LVCMOS compatible input as the reference clock signal. The PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The outputs can be disabled (high-impedance) by deasserting the OE/MR pin. In the PLL configuration with external feedback selected, deasserting OE/MR causes the PLL to loose lock due to missing feedback signal presence at FB_IN. Asserting OE/MR will enable the outputs and close the phase locked loop, enabling the PLL to recover to normal operation. The MPC9331 output clock stop control allows the outputs to start and stop synchronously in logic low state, without the potential generation of runt pulses. The MPC9331 is fully 3.3V compatible and requires no external loop filter components. The inputs (except PCLK) accept LVCMOS except signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the MPC9331 outputs can drive one or two traces giving the devices an effective fanout of 1:12. The device is packaged in a 7x7 mm2 32-lead LQFP package.
* * * * * *
Power_down feature reduces output clock frequency Drives up to 12 clock lines 32 lead LQFP packaging Ambient temperature range 0C to +70C Internal Power-Up Reset
FA SUFFIX 32 LEAD LQFP PACKAGE CASE 873A
W
(c) Motorola, Inc. 2003
MPC9331
VCC 3 x 25 K PCLK PCLK CCLK REF_SEL 25k FB_IN 25k VCC FB_SEL 25k VCC 25k PWR_DN VCC 25k 1 FB 0 /8 Bank A 0 1 Ref VCO /1 /2 0 1 1 0 /2 /4 /6 Bank B QB0 0 1 CLK STOP QB1 Bank C QC0 0 1 CLK STOP QC1 0 1 CLK STOP QA1 QA0
PLL
200-480 MHz
PLL_EN FSELA FSELB FSELC 3 x 25 K CLK_STOP0 CLK_STOP1 OE/MR VCC 3 x 25 K POWER_ON RESET 3
Figure 1. MPC9331 Logic Diagram
REF_SEL PLL_EN 18 FB_SEL GND VCC
QB0
QB1
24 GND QA1 QA0 VCC FSELA FSELB FSELC NC 25 26 27 28
23
22
21
20
19
NC 17 16 15 14 13 GND QC1 QC0 VCC FB_IN CLK_STOP1 CLK_STOP0 NC 12 11 10 9 8 GND
MPC9331
29 30 31 32 1 2 3 4 5 6 7
VCC_PLL
PWR_DN
CCLK
OE/MR
PCKL
It is recommended to use an external RC filter for the analog VCC_PLL power supply pin. Please see application section for details.
Figure 2. MPC9331 32-Lead Package Pinout (Top View)
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PCLK
NC
TIMING SOLUTIONS
MPC9331
Table 1. Pin Configuration
Pin CCLK PCLK, PCLK FB_IN FB_SEL REF_SEL PWR_DN FSELA FSELB FSELC PLL_EN CLK_STOP0-1 OE/MR QA0-1, QB0-1, QC0-1 GND VCC_PLL Input Input Input Input Input Input Input Input Input Input Input Input Output Supply Supply I/O Type LVCMOS LVPECL LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Ground VCC PLL reference clock signal Differential PECL reference clock signal PLL feedback signal input, connect to an output Feedback select Reference clock select Output frequency and power down select Frequency divider select for bank A outputs Frequency divider select for bank B outputs Frequency divider select for bank C outputs PLL enable/disable Clock output enable/disable Output enable/disable (high-impedance tristate) and device reset Clock outputs Negative power supply (GND) PLL positive power supply (analog power supply). It is recommended to use external RC filter for the analog power supply pin VCC_PLL. Please see applications section for details. Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation Function
VCC
Supply
VCC
Table 2. Function Table
Control REF_SEL FB_SEL PLL_EN Default 0 1 1 0 PCLK is the PLL reference clock Internal PLL feedback of 8. fVCO = 8 * fref Test mode with PLL disabled. The reference clock is substituted for the internal VCO output. MPC9331 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. VCO / 1 (High output frequency range) Output divider / 2 Output divider / 2 Output divider / 4 Outputs disabled (high-impedance state) and reset of the device. During reset in external feedback configuration, the PLL feedback loop is open. The VCO is tied to its lowest frequency. The MPC9331 requires reset after any loss of PLL lock. Loss of PLL lock may occur when the external feedback path is interrupted. The length of the reset pulse should be greater than one reference clock cycle (CCLK or PCLK). Reset does not affect PLL lock in internal feedback configuration. See Table 3 1 CCLK is the PLL reference clock External feedback. Zero-delay operation enabled for CCLK or PCLK as reference clock Normal operation mode with PLL enabled.
PWR_DN FSELA FSELB FSELC OE/MR
1 0 0 0 1
VCO / 2 (Low output frequency range) Output divider / 4 Output divider / 4 Output divider / 6 Outputs enabled (active)
CLK_STOP[0:1]
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PWR_DN, FSELA, FSELB and FSELC control the operating PLL frequency range and input/output frequency ratios. See Tables 8 - 10 for supported frequency ranges and output to input frequency ratios.
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Table 3. Clock Output Synchronous Disable (CLK_STOP) Function Table a
CLK_STOP0 0 0 1 1 a. CLK_STOP1 0 1 0 1 QA[0:1] Active Active Stopped in logic L state Active QB[0:1] Stopped in logic L state Stopped in logic L state Stopped in logic L state Active QC[0:1] Stopped in logic L state Active Active Active
Output operation for OE/MR=1 (outputs enabled). OE/MR=0 will high-impedance tristate all outputs independend on CLK_STOP[0:1]
Table 4. General Specifications
Symbol VTT MM HBM LU CPD CIN Characteristics Output termination voltage ESD protection (Machine model) ESD protection (Human body model) Latch-up immunity Power dissipation capacitance Input capacitance 200 2000 200 10 4.0 Min Typ VCC / 2 Max Unit V V V mA pF pF Per output Inputs Condition
Table 5. Absolute Maximum Ratingsa
Symbol VCC VIN VOUT IIN IOUT Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Characteristics Min -0.3 -0.3 -0.3 Max 3.9 VCC + 0.3 VCC + 0.3 20 50 Unit V V V mA mA Condition
TS Storage temperature -65 125 C a Absolute maximum continuos ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied.
Table 6. DC Characteristics (VCC = 3.3V 5%, TA = 0C to +70C)
Symbol VIH VIL VPP VCMRa VOH VOL ZOUT IIN ICC_PLL a Characteristics Input high voltage Input low voltage Peak-to-peak input voltage Common Mode Range Output High Voltage Output Low Voltage Output impedance Input Currentc Maximum PLL Supply Current 8.0 14 - 17 200 12 PCLK, PCLK PCLK, PCLK 250 1.0 2.4 0.55 0.30 VCC - 0.6 Min 2.0 Typ Max VCC + 0.3 0.8 Unit V V mV V V V V A mA VIN = VCC or GND VCC_PLL Pin Condition LVCMOS LVCMOS LVPECL LVPECL IOH = -24 mAb IOL = 24 mA IOL = 12 mA
ICCQ Maximum Quiescent Supply Currentd 26 mA All VCC Pins VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification b The MPC9331 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. c Inputs have pull-down or pull-up resistors affecting the input current. d OE/MR=0 (outputs in high-impedance state).
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Table 7. AC Characteristics (VCC = 3.3V 5%, TA = 0C to +70C)a
Symbol fREF Characteristics Input reference frequency PLL mode, external feedback /2 feedback /4 feedback /6 feedback /8 feedback /12 feedback PLL mode, internal feedback (/8 feedback) Input reference frequency in PLL bypass modeb /2 output /4 output /6 output /8 output /12 output PCLK, PCLK PCLK, PCLK Min 100.0 50.0 33.3 25.0 16.67 25.0 200 100.0 50.0 33.3 25.0 16.67 400 1.2 2.0 1.0 -250 -180 -3.0 -130 -30 -50 +120 +3.0 150 (TB2)-500 0.1 TB2 (TB2)+500 1.0 8.0 10 200 125 RMS (1 ) / 4 feedback / 6 feedback / 8 feedback /12 feedback 2.0-8.0 1.2-4.0 1.0-3.0 0.7-2.0 10 25 Typ Max 240.0 120.0 80.0 60.0 40.0 60.0 240 480 240.0 120.0 80.0 60.0 40.0 1000 VCC - 0.9 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz mV V ns ns ps ps 0.8 to 2.0V FB_SEL = 1 and PLL locked PLL locked Condition PLL locked
fVCO fMAX
VCO lock frequency rangec Output Frequency
VPP VCMRd tPW,MIN tR, tF t()
Peak-to-peak input voltage Common Mode Range Input Reference Pulse Widthe CCLK Input Rise/Fall Timef Propagation Delay (static phase offset) Output-to-output Skew Output duty cyclei Output Rise/Fall Time Output Disable Time Output Enable Time Cycle-to-cycle jitterj Period Jitterj I/O Phase Jitter PLL closed loop bandwidthk PLL mode, external feedback
LVPECL LVPECL
CCLK to FB_INg PCLK to FB_INg CCLK or PCLK to FB_INh
tsk(O) DC tR, tF tPLZ, HZ tPZL, LZ tJIT(CC) tJIT(PER) tJIT() BW
ps ps ns ns ns ps ps ps MHz MHz MHz MHz ms 0.55 to 2.4V
tLOCK
Maximum PLL Lock Time
NOTES: a AC characteristics apply for parallel output termination of 50 to VTT. b In bypass mode, the MPC9331 divides the input reference clock. c The input frequency fREF must match the VCO frequency range divided by the feedback divider ratio FB: fREF = fVCO / FB. d VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(). e Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN fREF 100% and DCREF,MAX = 100% - DCREF,MIN. f The MPC9331 will operate with input rise/fall times up to 3.0 ns, but the AC characteristics, specifically t(), tPW,MIN, DC and fMAX can only be guaranteed if tR, tF are within the specified range. g Data valid for fREF=50 MHz and a PLL feedback of /8 (e.g. QAx connected to FB_IN and FSELA=1, PWR_DN=1). h Data valid for 16.67 MHz < fREF < 100 MHz and any feedback divider. tsk(O) [s] = tsk(O) [] / (fREF 360). i Output duty cycle is DC = (0.5 500 ps fOUT) 100%. (e.g. the DC range at fOUT = 100 MHz is 45% < DC < 55%). j All outputs in /4 divider configuration. k -3 dB point of PLL transfer characteristics.
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MPC9331
APPLICATIONS INFORMATION
Output power down (PWR_DN) timing diagram
VCO/2 VCO/4 PWR_DWN QAx (/2) QBx (/4) QBCx (/6)
Output clock stop (CLK_STOP) timing diagram
QAx (/2) QBx (/4) QCx (/6)
CLK_STOP0 CLK_STOP1 QAx (/2) QBx (/4) QCx (/6)
Programming the MPC9331 The MPC9331 supports output clock frequencies from 16.67 to 240 MHz. Different feedback and output divider configurations can be used to achieve the desired input to output frequency relationship. The feedback frequency and divider should be used to situate the VCO in the frequency lock range between 200 and 480 MHz for stable and optimal
operation. The FSELA, FSELB, FSELC and PWR_DN pins select the desired output clock frequencies. Possible frequency ratios of the reference clock input to the outputs are 4:1, 3:1, 2:1, 1:1, 1:2, 2:3 and 3:2. Table 8 illustrates the various output configurations and frequency ratios supported by the MPC9331. See also Table 8 and 9 for further reference.
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Table 8. MPC9331 Example Configurations (Internal Feedback and FB_SEL = 0)
frefa [MHz] PWR_DN 0 0 0 0 0 0 0 25.0 - 60.0 0 1 1 1 1 1 1 1 1 a. FSELA 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FSELB 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FSELC 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 QA[0:1]:fref ratio fref 4 (100-240 MHz) fref 4 (100-240 MHz) fref 4 (100-240 MHz) fref 4 (100-240 MHz) fref 2 (50-120 MHz) fref 2 (50-120 MHz) fref 2 (50-120 MHz) fref 2 (50-120 MHz) fref 2 (50-120 MHz) fref 2 (50-120 MHz) fref 2 (50-120 MHz) fref 2 (50-120 MHz) fref fref fref fref (25.0-60 MHz) (25.0-60 MHz) (25.0-60 MHz) (25.0-60 MHz) QB[0:1]:fref ratio fref 4 (100-240 MHz) fref 4 (100-240 MHz) fref 2 (50-120 MHz) fref 2 (50-120 MHz) fref 4 (100-240 MHz) fref 4 (100-240 MHz) fref 2 (50-120 MHz) fref 2 (50-120 MHz) fref 2 (50-120 MHz) fref 2 (50-120 MHz) fref fref (25.0-60 MHz) (25.0-60 MHz) QC[0:1]:fref ratio fref 2 (50-120 MHz) fref 4/3 (33.3-80 MHz) fref 2 (50-120 MHz) fref 4/3 (33.3-80 MHz) fref 2 (50-120 MHz) fref 4/3 (33.3-80 MHz) fref 2 (50-120 MHz) fref 4/3 (33.3-80 MHz) fref fref fref fref (25.0-60 MHz) (25.0-60 MHz) (25.0-60 MHz) (25.0-60 MHz) fref 2/3 (16.67-40 MHz) fref 2/3 (16.67-40 MHz) fref 2/3 (16.67-40 MHz) fref 2/3 (16.67-40 MHz)
fref 2 (50-120 MHz) fref 2 (50-120 MHz) fref fref (25.0-60 MHz) (25.0-60 MHz)
fref is the input clock reference frequency (CCLK or PCLK)
Table 9. MPC9331 Example Configurations (External Feedback and PWR_DN = 0)
PLL Feedback frefa [MHz] 100 - 240 VCO / 2b FSELA 0 0 0 0 50 - 120 VCO / 4c 1 1 1 1 33.3-80 VCO / 6d 0 0 1 1 a. b. c. d. FSELB 0 0 1 1 0 0 1 1 0 1 0 1 FSELC 0 1 0 1 0 1 0 1 1 1 1 1 QA[0:1]:fref ratio fref fref fref fref fref fref fref fref fref 3 fref 3 (100-240 MHz) (100-240 MHz) (100-240 MHz) (100-240 MHz) (50-120 MHz) (50-120 MHz) (50-120 MHz) (50-120 MHz) (100-240 MHz) (100-240 MHz) QB[0:1]:fref ratio fref fref (100-240 MHz) (100-240 MHz) QC[0:1]:fref ratio fref / 2 (50-120 MHz) fref / 3 (33.3-80 MHz) fref / 2 (50-120 MHz) fref / 3 (33.3-80 MHz) fref fref fref fref fref fref (50-120 MHz) (50-120 MHz) (33.3-80 MHz) (33.3-80 MHz) (33.3-80 MHz) (33.3-80 MHz) fref 2/3 (33.3-80 MHz) fref 2 / 3 (33.3-80 MHz)
fref / 2 (50-120 MHz) fref / 2 (50-120 MHz) fref 2 fref 2 fref fref fref 3 fref 3 (100-240 MHz) (100-240 MHz) (100-240 MHz) (100-240 MHz) (100-240 MHz) (100-240 MHz)
fref 3 / 2 (50-120 MHz) fref 3 / 2 (50-120 MHz)
fref 3 / 2 (50-120 MHz) fref 3 / 2 (50-120 MHz)
fref is the input clock reference frequency (CCLK or PCLK) QAx connected to FB_IN and FSELA = 0, PWR_DN = 0 QAx connected to FB_IN and FSELA = 1, PWR_DN = 0 QCx connected to FB_IN and FSELC = 1, PWR_DN = 0 frefa [MHz] 25.0 - 60.0 VCO / 8b
Table 10. MPC9331 Example Configurations (External Feedback and PWR_DN = 1)
PLL Feedback FSELA 1 1 1 1 16.67 - 40 VCO / 12c 0 0 1 1 a. b. c. FSELB 0 0 1 1 0 1 0 1 FSELC 0 1 0 1 1 1 1 1 QA[0:1]:fref ratio fref fref fref fref fref 3 fref 3 (25-60 MHz) (25-60 MHz) (25-60 MHz) (25-60 MHz) (50-120 MHz) (50-120 MHz) QB[0:1]:fref ratio fref 2 fref 2 fref fref fref 3 fref 3 (50-120 MHz) (50-120 MHz) (25-60 MHz) (25-60 MHz) (50-120 MHz) (50-120 MHz) fref fref fref fref fref fref QC[0:1]:fref ratio (2.25-60 MHz) (25-60 MHz) (16.67-40 MHz) (16.67-40 MHz) (16.67-40 MHz) (16.67-40 MHz)
fref 2/3 (16.6-40 MHz) fref 2/3 (16.6-40 MHz)
fref 3 / 2 (25-60 MHz) fref 3 / 2 (25-60 MHz)
fref 3 / 2 (25-60 MHz) fref 3 / 2 (25-60 MHz)
fref is the input clock reference frequency (CCLK or PCLK) QAx connected to FB_IN and FSELA = 1, PWR_DN = 1 QCx connected to FB_IN and FSELC = 1, PWR_DN = 1
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MPC9331
APPLICATIONS INFORMATION
Power Supply Filtering The MPC9331 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCC_PLL power supply impacts the device characteristics, for instance I/O jitter. The MPC9331 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCC_PLL) of the device.The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCC_PLL pin for the MPC9331. Figure 7 illustrates a typical power supply filter scheme. The MPC9331 frequency and phase stability is most susceptible to noise with spectral content in the 100 kHz to 20 MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICC_PLL current (the current sourced through the VCC_PLL pin) is typically 8 mA (12 mA maximum), assuming that a minimum of 3.0V must be maintained on the VCC_PLL pin.
RF = 10-15 RF VCC CF 10 nF CF = 22 F VCC_PLL MPC9331 VCC 33...100 nF MPC9331 OUTPUT BUFFER IN
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Driving Transmission Lines The MPC9331 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Motorola application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9331 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 4 "Single versus Dual Transmission Lines" illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9331 clock driver is effectively doubled due to its capability to drive multiple lines.
MPC9331 OUTPUT BUFFER IN
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RS = 36
ZO = 50 OutA
RS = 36
ZO = 50 OutB0
Figure 3. VCC_PLL Power Supply Filter The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in Figure 3, the filter cut-off frequency is around 3-5 kHz and the noise attenuation at 100 kHz is better than 42 dB. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC9331 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs.
RS = 36
ZO = 50 OutB1
Figure 4. Single versus Dual Transmission Lines The waveform plots in Figure 5 "Single versus Dual Line Termination Waveforms" show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9331 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9331. The output waveform in Figure 5 "Single versus Dual Line Termination Waveforms" shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 series resistor plus the output
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impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS ( Z0 / (RS+R0 +Z0)) Z0 = 50 || 50 RS = 36 || 36 R0 = 14 VL = 3.0 ( 25 / (18+14+25) = 1.31V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.6V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns). 1 Final skew data pending specification.
3.0 OutA tD = 3.8956 OutB tD = 3.9386
Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 6 "Optimized Dual Line Termination" should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched.
MPC9331 OUTPUT BUFFER
14
RS = 22
ZO = 50
RS = 22
ZO = 50
2.5
VOLTAGE (V)
2.0 In 1.5
14 + 22 k 22 = 50 k 50 25 = 25 Figure 6. Optimized Dual Line Termination
1.0
0.5
0 2 4 6 8 TIME (nS) 10 12 14
Figure 5. Single versus Dual Waveforms
MPC9331 DUT Pulse Generator Z = 50W ZO = 50 ZO = 50
RT = 50 VTT
RT = 50 VTT
Figure 7. CCLK MPC9331 AC test reference for Vcc = 3.3V
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MPC9331
VCC VCC VCC VCC
B2
CCLK
GND
B2
FB_IN
VCC VCC VCC VCC
B2 B2
GND
GND tSK(O) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device
GND t()
Figure 8. Output-to-output Skew tSK(O)
VCC VCC tP T0 DC = tP /T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage
Figure 9. Propagation delay (t(), static phase offset) test reference
CCLK
B2
GND FB_IN
TJIT() = |T0 -T1 mean| The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles
Figure 10. Output Duty Cycle (DC)
Figure 11. I/O Jitter
TN
TN+1
TJIT(CC) = |TN -TN+1 |
T0
TJIT(PER) = |TN -1/f0 |
The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs
The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles
Figure 12. Cycle-to-cycle Jitter
Figure 13. Period Jitter
VCC=3.3V 2.4 0.55 tF tR
Figure 14. Output Transition Time Test Reference
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OUTLINE DIMENSIONS
FA SUFFIX LQFP PACKAGE CASE 873A-02 ISSUE A
A A1
32 25 4X
0.20 (0.008) AB T-U Z
1
-T- B B1
8
-U- V DETAIL Y
17
V1
9
-Z- 9 S1 S
4X
0.20 (0.008) AC T-U Z
NOTES: 1 DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION: MILLIMETER. 3 DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4 DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5 DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6 DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7 DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8 MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9 EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION.
-T-, -U-, -Z-
G -AB-
SEATING PLANE
DETAIL AD
-AC- 0.10 (0.004) AC AE
8X
M_ R
P AE
CE
DETAIL Y
GAUGE PLANE
0.250 (0.010)
H
W X DETAIL AD
K
Q_
BASE METAL
N
F
D
J
SECTION AE-AE
TIMING SOLUTIONS
11
0.20 (0.008)
M
AC T-U Z
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF
INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
EE EE EE
MOTOROLA
MPC9331
Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are the property of their respective owners.
E Motorola Inc. 2003
HOW TO REACH US: USA / EUROPE / LOCATIONS NOT LISTED: TECHNICAL INFORMATION CENTER: 1-800-521-6274 or 480-768-2130 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu, Minato-ku, Tokyo 106-8573 Japan 81-3-3440-3569 ASIA / PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2, Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852-26668334 HOME PAGE: http://motorola.com/semiconductors
MOTOROLA
12
MPC9331/D TIMING SOLUTIONS

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